This page was last modified 14:28, 9 June 2022 by Gdx. Based on work by Lintweaker and Keith and others.



The Z80180 is an 8-bit MPU which provides the benefits of reduced system costs and also provides full backward compatibility with existing Zilog Z80 devices. Reduced system costs are obtained by incorporating several key system functions on-chip with the CPU. These key functions include I/O devices such as DMA, UART, and timer channels. Also included on-chip are wait-state generators, a clock oscillator, and an interrupt controller. The Z80180 is housed in 80-pin QFP, 68-pin PLCC, and 64-pin DIP packages.

No MSX are equiped with the Z80180 except the Victor HC-90/95 which are equipped with the HD64180 whose Zilog based itself to make the Z80180. So the HD64180 can be considered as the first CPU of the Z180 family.


Architecture The Z180® combines a high-performance CPU core with a variety of system and I/O resources useful in a broad range of applications:

  • Central Processing Unit: The CPU is microcoded to provide a core that is object-code compatible with the Z80 CPU. It also provides a superset of the Z80 instruction set, including 8-bit multiply. The core is modified to allow many of the instructions to execute in fewer clock cycles.
  • Memory Management Unit: The MMU allows you to map the memory used by the CPU (logically only 64 KB) into the 1-MB addressing range supported by the Z80180. The organization of the MMU object code allows maintenance compatibility with the Z80 CPU, while offering access to an extended memory space. This organization is achieved by using an effective common area-banked area scheme.
  • DMA Controller: The DMA controller provides high speed transfers between memory and I/O devices. Transfer operations supported are memory-to-memory, memory to/from I/O, and I/O-to-I/O. Transfer modes supported are request, burst, and cycle steal. DMA transfers can access the full 1 MB address range with a block length up to 64 KB, and can cross over 64K boundaries.
  • Asynchronous Serial Communication Interface (ASC): The ASCI logic provides two individual full-duplex UARTs. Each channel includes a programmable baud rate generator and modem control signals. The ASCI channels also support a multiprocessor communication format as well as break detection and generation.
  • Programmable Reload Timers (PRT): This logic consists of two separate channels, each containing a 16-bit counter (timer) and count reload register. The time base for the counters is derived from the system clock (divided by 20) before reaching the counter.
  • Clock Generator: Generates system clock from an external crystal or clock input. The external clock is divided by two or one and provided to both internal and external devices.
  • Bus State Controller: This logic performs all of the status and bus control activity associated with both the CPU and some on-chip peripherals. Included are wait-state timing, reset cycles, DRAM refresh, and DMA bus exchanges.
  • Interrupt Controller: This logic monitors and prioritizes the variety of internal and external interrupts and traps to provide the correct responses from the CPU. To maintain compatibility with the Z80® CPU, three different interrupts modes are supported.

It is not fully backwards compatible with the Z80 though, because the 00H-3FH I/O address space is reserved for internal functions (*), and the undocumented IXH/IXL instructions are not functional.

This processor was used in at least four MSX computers: Mitsubishi ML-TS100, Mitsubishi ML-TS100M2, Victor HC-90 and Victor HC-95, all MSX2 computers, running at 6,144 MHz, in addition to a 3.58 MHz Z80 for compatibility.

(*) The internal I/O addresses can be remapped but will always overlap with existing MSX hardware


The Zilog Z80182 is an enhanced, faster version of the older Z80 and is part of the Z180 microprocessor family. It's nicknamed the Zilog Intelligent Peripheral Controller (ZIP). It's also fully static (the clock can be halted and no data in the registers will be lost) and has a low EMI option that reduces the slew rate of the outputs.

The Z80182 can operate at 33 MHz with an external oscillator for 5-volt operation, or at 20 MHz using the internal oscillator for 3.3-volt operation

List of Models

Many versions were made, but this processor didn’t gain much attention from MSX companies.

Chip Speed (MHz) Timers I/O Comm. Contr. Others
Z80180 6, 8, 10 2 N/S CPU 1 MB MMU, 2xDMAs, 2xUARTs
Z80181 10 1 16 CPU 1 MB MMU, 2xDMAs, 2xUARTs
Z80182 16, 33, 20 0 Clock Serial, 24 ESCC, CSIO, UART S180 Megacell, 2xESCC channels, 16550 MIMIC
Z80195 20, 33 4 7/24 SCC, CSIO, UART
Z8L180 20 2 Clock Serial CSIO, UART 1 MB MMU, 2xDMAs, 2xUARTs, 3.3 V Operation
Z8L182 20 0 Clock Serial ESCC, CSIO, UART S180 Megacell, 2xESCC channels, 16550 MIMIC, 3.3V operation
Z8S180 10, 20, 33 2 Clock Serial UART, DMA, Timers 1 MB MMU, 2xDMAs, 2xUARTs


Z80180 Functional Diagram.png


More information about the Zilog Z180 can be found here: