Pretty cool. I would expect that in some scene changes almost the whole screen would need a refresh. If that doesn't happen to often, the VDP and CPU might keep things at 30fps indeed. But it's still quite amazing. (How long does it take again to refresh a screen 5 page of 32kB?)
At its fastest a complete fill of 24K VRAM takes 124 ms (3.7 frames @ 30 Hz) on Z80 and 220 ms (6.6 frames @ 30 Hz) on R800. It will be slower here because this demo also outputs PCM audio. I don’t know if the audio syncs to HR (the frequency suggests that it does), and whether it uses R800 mode (probably faster if it doesn’t).
Ryun explains more here: https://twitter.com/r_y_u_n/status/1296608963278942208
Can anyone also please explain how the PCM play works on the OPLL?
I read it keeps Phase at a certain level, by using the test register bit 2, but that is not enough explanation for me. ;-)
In the source code I cannot immediately see what that trick is here. Grauw, can you be a bit more elaborate how you made that work ? Is this using register 0f of the OPLL? Is that comparable with register 01 on the OPL2?
Hi Mr.Mouse, see my posts in this thread, as well as D.S.A.’s explanation. If you have any further questions let me know!
The other OPLs should also have the same test register function (in register 1 instead of register 15), however you need to double the setting for the multiplier because they have one more phase bit than the OPLL. Because a multiplier of 24 can’t be set, only the technique with dc-offset can be used.
Impressive. VERY impressive. And all of this on our humble MSX...
Is there a way to get my hands on the complete set of files?
Manuel Pazos also posted a Bad Apple FMV on twitter:
New Bad Apple video (Z80, SCREEN 5 256x192, about 30 fps, PCM 15.7 kHz played using the OPLL)
It uses the MSX-MUSIC to play the PCM. It also seems to use a new function of the MegaFlashROM SCC+ SD FPGA (needs to be updated I think), I’m guessing it’s for streaming data from disk?
I actually heard about this before. Really impressive on a TI calc. Hopefully an MSX version comes along.
Is there a way to get my hands on the complete set of files?
- First play the video here : https://www.nicovideo.jp/watch/sm8628149
- Enable the devlopper mode of your browser (firefox or Chrome)
- Right click the the video and select 視聴方法の切替え (to set http/hls).
- Search the video file in the devlopper frame (>4MB) and open it in a new tab (right click)
- Rename the downloaded video "BadApple.MP4" for example.
- Then use these tools to convert the video : http://ryun.halfmoon.jp/msx/badapple/
Hi Mr.Mouse, see my posts in this thread, as well as D.S.A.’s explanation. If you have any further questions let me know!
The other OPLs should also have the same test register function (in register 1 instead of register 15), however you need to double the setting for the multiplier because they have one more phase bit than the OPLL. Because a multiplier of 24 can’t be set, only the technique with dc-offset can be used.
I do have some more questions, can I email you? :)