One chip MSX improvement project

As for the scale of FPGA, I think there is capacity to implement R800.
I think that the same access as R800 is difficult because of SDRAM access problem.

Even though SDRAM has a lot of command overhead, it is structured to be accessed from both the CPU and VDP at about 4x speed.
The only idea is to create a new FPGA board with separate CPU SDRAM and VDP SDRAM, or clock up more.
In order to manage with the current device, it is necessary to raise the clock, but the current double speed exceeds the SDRAM specification.
I want to carefully consider how to respond.

So tha main problem if I understood right would be at that using the same SDRAM pool and cannot set different waits for CPU and VDP accesses.