Indeed there is a mapping from the instrument to a specifc 'region' i.e. per range of notes there is another region of an instrument to be played (to overcome the samples are stretched too much from very low to very high frequencies). The file mentioned in the linux driver provides the table to perform this mapping, based on instrument number and note number.
The first and second value on every line indicates the range of note numbers it is applicable to, the region table name itself is the number of the GM instrument.
The Linux driver is ordered by GM instrument number, and then it specifies instrument settings per note range:
{0x14, 0x2d, {0x12c,7474,100, 0,0,0x00,0xc8,0x20,0xf2,0x13,0x08,0x0}},
The 0x14 and 0x2d are note regions, and then the part that follows are instrument settings. I think the first number (0x12c in this case) is the instrument number in the ROM.
Thanx !
This makes implementing these instruments in a DAW even more complicated.
Not only do I need to add several samples per instrument. I also need to convert them to their own unique frequency in my replayer... Wow.
Well... it's keeping me busy
Hey, where would be the fun if it was easy
Another thing I noticed is when outing values to the moonsound registers, I should not out too fast... Is that correct ?
I found nops in between out instructions in the original code:
ld a,b ;channel number add a,$20 ;register number out (pcm_reg),a ;frequency inc de ;f-number, octave ld a,(de) nop nop out (pcm_data),a
How much time exactly do I need to wait between out instructions ?
I was wondering for instance if this code would be viable on a real msx (it works in an emulator)
ld c,pcm_data ld a,(hl) ;register number out (pcm_reg),a inc hl ;data outi
Currently no MSX emulators take too fast access to OPL4 into account. So please be careful.
I found this in the Moonsound manual:
address write mode:
in this mode, a write address is specified
set the register address onto this data bus.
to write or read data after the address is written, a master clock wait of
FM register........ 56 cycles
PCM, MIX register.. 88 cycles
is necessary
But how do i translate this to Tstates ?
A nop instruction for instance takes 1 M cycle and 4 Tstates (4 MHz E.T. = 1 ??) according to the z80 manual.
Ignore the Z80 M cycles, they are not very useful for timing info. The T-states mentioned in the Z80 manual are clock cycles from the 35879545 Hz clock, just under a different name.
The cycles mentioned in the OPL4 manual are clock cycles, but relative to the OPL4 clock. As you can see on page 6 (PDF page 9) of the OPL4 manual, the OPL4 master clock is 33868800 Hz. So the waits must be 56 / 33868800 = 1.65 µs and 88 / 33868800 = 2.60 µs respectively.
In Z80 clock cycles this translates to 56 / 33868800 * 3579545 = 5.92 Z80 cycles and 88 / 33868800 * 3579545 = 9.30 Z80 cycles @ 3.58 MHz. On the turboR turbo mode that is 56 / 33868800 * 7159091 = 11.84 R800 cycles and 88 / 33868800 * 7159091 = 18.60 R800 cycles @ 7.16 MHz.
And then you put your Z80 in turbo mode (Z80B) and...
All that about timmings are a pain in the *ss, having the CPU a WAIT pin, and the MSX slot also a WAIT signal, too bad it's never used by any device. The software itself should not care about those matters and more in a multi-configuration environment, like the MSX is.
The only solution I see is to standardize things. Collaborative drivers and sources prepared for all machines, but made once, then anyone who require it would get from there, updated and fixed at that moment.
I normally use the BUSY (for FM) and LD (for Wave) flags of the status register provided by the OPL4 itself. For regular Z80 this is already most likely overkill but at least the CPU speed is completely out of the picture. Note that you do need to put the NEW2 flag on (so put it in 'OPL4 mode') in order to make this work.
So far this gave no problems on real HW (Turbo-R and MSX2+). The emulators indeed should not be trusted for this.