I can't think of anything sounding better than HDMI, digitally generated audio being carried over a digital connection.... Can it get any better? 
Agree, but I don't have any idea yet how do i extract audio from HDMI to pass it to my audio mixer, so for me using HDMI for enjoying audio is not an option (yet of course digital audio should be bestest quality of course). So i'm more concerned about 3.5 mm audio jack output 
I was just wondering, with the space left, what kind of components could in theory be done? I imagine that OPL4 would be too much for the space left, but I wonder, would V9990 be possible?
There are about 9K logic units free, considering that an OPL3 FPGA implementation already exists and perhaps it could be done as a replacement of the OPLL code (a superset of it)... Not sure how large would it be the PCM part of OPL4, that is basically the difference between OPL4 and OPL3... My guess is that it is doable, as someone already did an OPL3 on FPGA, there is plenty of RAM to be used as well...
But, again, people need to step in and work on stuff, one guy alone can do so much on free time, since I really dig into bringing MSX to the internet, I've been working with it, learned a lot on the process (did know 0 about UNAPI, TCP/IP and FPGA, Konamiman and Victor did help me when I've asked stuff to understand and get the work done)... More people need to volunteer and start working on different stuff, that is when the magic will start to happen.
Any ideas of what to do with the extra space in the FPGA of this machine?
This larger FPGA is perfect for projects like "MoeSX" by TNI
http://www.tni.nl/news/msx-35th-anniversary-%E8%90%8C%EF%BD%...
or
https://www.msx.org/news/en/updates-on-%E8%90%8C%EF%BD%93%EF...
The main idea/first step is to create it in FPGA form
They aim for r800/v9990 compatibility but as i mentioned in my reply to that mrc newspost one of the hurdles is to make it fit into a 1chipmsx/zemmix neo sized fpga chip (to make it available to a broader audience), but if more device like the MSx-SM appear with more fpga space, that problem may be solved.
