Graphically impressive z80 machine | MSX Resource Center (Pagina 4/6)

Prophet (2927)

31-12-2018, 16:27

Quote:

On the Z80, the HL is used as a 16bit accumulator by many instructions

but. it does not serve as a 16bit akku in RAM to RAM ops:

        ;16bit X = X + DX

        ld a,(de)
        add (hl)
        ld (hl),a
        inc de
        inc hl
        ld a,(de)
        adc (hl)
        ld (hl),a

trying to use 16bit ADD would make things slower, funny
RAM to RAM ops are important, move sprites and polygons.

now look this:

        ;memory layout: DXL DXH XL XH. DE points to DXL
        
        ld hl,2
        add hl,de       ;HL points to XL
        ld a,(de)
        add (hl)
        ld (hl),a
        inc de
        inc hl
        ld a,(de)
        adc (hl)
        ld (hl),a

a 16bit ADD could be added just as a tiny little sidenote, very funny! the ADD was about ADDRESSES.

so. HL is no good 16bit akku. but a full 16bit address register.
this code for some scaled index

        ADD HL,HL
        ADD HL,HL
        ADD HL,DE

this is 3 opcode bytes. while on the 6502 it would be 36 bytes!!!

Van Manel46

Paladin (674)

31-12-2018, 19:05

Imagine what the equivalent of LDIR would be with the 6502, 6510 (C64)
The 6502 only has a 16 bit register, the PC.

Van PingPong

Prophet (4093)

31-12-2018, 23:18

hit9918 wrote:

Quote:

On the Z80, the HL is used as a 16bit accumulator by many instructions

but. it does not serve as a 16bit akku in RAM to RAM ops:

        ;16bit X = X + DX

        ld a,(de)
        add (hl)
        ld (hl),a
        inc de
        inc hl
        ld a,(de)
        adc (hl)
        ld (hl),a

trying to use 16bit ADD would make things slower, funny
RAM to RAM ops are important, move sprites and polygons.

now look this:

        ;memory layout: DXL DXH XL XH. DE points to DXL
        
        ld hl,2
        add hl,de       ;HL points to XL
        ld a,(de)
        add (hl)
        ld (hl),a
        inc de
        inc hl
        ld a,(de)
        adc (hl)
        ld (hl),a

a 16bit ADD could be added just as a tiny little sidenote, very funny! the ADD was about ADDRESSES.

so. HL is no good 16bit akku. but a full 16bit address register.
this code for some scaled index

        ADD HL,HL
        ADD HL,HL
        ADD HL,DE

this is 3 opcode bytes. while on the 6502 it would be 36 bytes!!!

Let's imagine how slower would be a LDIR on 6502.... ;-)

Van keith56

Master (162)

01-01-2019, 00:40

For anyone interested, I created a 'fake' LDIR command during my 'Grime 6502' project... using the Zero page to simulate Z80 registers... the result is below, I'm not claiming it's the fastest way to do the job on the 6502, but it does work.

LDIR:
		ldy #0
		lda (z_HL),Y
		sta (z_DE),Y
		INC z_L
		BNE	LDIR_SkipInc1
		INC	z_H
LDIR_SkipInc1:
		INC z_E
		BNE	LDIR_SkipInc2
		INC	z_D
LDIR_SkipInc2:
		DEC z_C
		BNE LDIR
		LDA z_B
		BEQ	LDIR_Done
		DEC z_B
		jmp LDIR
LDIR_Done:

Van Manel46

Paladin (674)

01-01-2019, 12:27

LDX #n
LOOP:
TXA
PHA
;WORK
PLA
TAX
DEX
BNE LOOP

I do not remember much. This would be equivalent to DJNZ?
Instead of using X, you can use memory on page zero.

Van keith56

Master (162)

01-01-2019, 12:30

And just so we can all laugh at the 6502, here's the LDIR command on the 68000!

LDIR:
	move.b (a3)+,(a2)+
	dbra d1,LDIR

Van -LeoN-

Rookie (22)

01-01-2019, 16:02

The 65816 has MVN/MVP instructions of LDIR analog. It runs at 7 clocks per byte!

Van Grauw

Ascended (10706)

01-01-2019, 16:50

At first sight the 6502 architecture with that page zero sounds nice, like 256 registers right. But then when I see code for it I’m glad I’m dealing with the Z80 . 6502 is a bit too RISC-y for my liking, code seems very verbose. Saying this as a complete 6502 n00b of course.

Van Manel46

Paladin (674)

01-01-2019, 17:05

Without discussion, Z80.
Years ago, I programmed 6502, that knowing Z80, I found it easier.

Van TomH

Champion (340)

02-01-2019, 20:20

keith56 wrote:

For anyone interested, I created a 'fake' LDIR command during my 'Grime 6502' project... using the Zero page to simulate Z80 registers... the result is below, I'm not claiming it's the fastest way to do the job on the 6502, but it does work. [..]

Not that you were asking, but switching at least one of those to (ind, x) and incrementing X rather than a byte in memory would save a small amount (as the faster increment outweighs the slower addressing mode). If were to do the classic 6502 thing of page aligning as much as possible, including all potential sources and targets, you could obviously save a bit more by doing one test for carry rather than two, orthogonally to addressing mode.

The 65C02 added unindexed indirect addressing, but not for INC and DEC. Indeed the 65C02 designers seem to have hated INC and DEC in general; all of the other abs,X instructions are a cycle faster on that iteration if they don't cross a page boundary but INC and DEC aren't.

... and this sort of thing is the reason that the C64 was usually worse for isometric and 3d titles, isn't it? In extremis see titles like Carrier Command, a solid 3d title on the CPC and Spectrum and an overhead 2d title on the C64. Or the terrible Hard Drivin' port, but that sounds more like botched project management and scrambling to release something.