MSX Turbo-R behavior with 1MB external mapper

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Par l_oliveira

Hero (532)

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14-02-2016, 13:51

Here,s how it works on the Turbo-R:

S1990 controls 1MB of memory maximum (Both ROM and RAM). Those are dealt with as a single pool of memory which can be assigned to the slots through writes on the S1990 chip configuration registers. The mapper port in S1990 is write only.

When you read mapper I/O ports you get return from the Toshiba engine. Because that supports only 512KB, you only get five bits read back. As RetroTechie explains, unused bits are left disconnected and will return the usual "1" that open bus defaults to on MSX computers (due to BUS pullups).

This is the circuit I use on my A1ST to implement the sixth bit:

74LS670 is tri-state bus, with a output enable pin, (74LS170 is similar but open collector) so the 74LS367 is redundant and I removed it.

/M1 is put on the equation of I/O decode logic to avoid triggering spurious accesses if someone switches the Z80 out of IM1 mode which is not a recommended practice in the MSX standard, but the hardware should have means of avoiding issues with.

Par sd_snatcher

Prophet (3498)

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14-02-2016, 14:37

Quote:

If the unused mapper bits aren't driven, then any tri-state output should do to put a value on the data lines. But if circuitry in the Turbo-R actively drives unused bits to some logic level, then you'd need an IC that can deliver more output current to 'overpower' that Turbo-R's circuitry. 74LS367 is such an IC ("buffer"), so maybe it was used for that reason?

AFAIK, if that was the case, it would be asking to fry the S1990 D5 bit, isn't it? From what I can remember chips don't tolerate well this kind of output war.

RetroTechie wrote:

Nope. For detecting reads/writes to I/O ports, you don't need /M1. Yes if you only want a signal that says "I/O ports xyz are accessed" then you'd need to include /M1 in the decoding circuit. But usually you combine such a signal with /RD or /WR, and in that case you can skip using /M1. That's because in the special case of /M1 and /IORQ going active (interrupt acknowledge but no I/O port access), /RD and /WR both stay high.

Yes, you're right. /M1 is only needed when you need to check I/O operations regardless if they're read or write. But it can also be used to simplify the I/O decoder circuit and use less logic gates. I.e.: /M1 can be directly connected to the pin-6 of an 74LS138 without any other extra logic.

Par l_oliveira

Hero (532)

Portrait de l_oliveira

14-02-2016, 14:38

Like I said, /M1 is used to make sure only I/O operations are going to cause the condition which enables the device. In a interrupt mode other than IM1 that can happen.

If the machine is kept all the time into IM1 mode, indeed there's no need to put /M1 into the logic. But we know that's not always the case.

Par sd_snatcher

Prophet (3498)

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14-02-2016, 14:42

@l_oliveira

Nice design! This is what I had in mind when I thought that the original circuit could be optimized. But since you already have done it, I ask your permission to use this design on a new board.

Following RetroTechie tips, /M1 and /MREQ could be eliminated from this decoder to minimize the amount of wires connected to the mobo, couldn't they?

Par l_oliveira

Hero (532)

Portrait de l_oliveira

14-02-2016, 14:45

I just said you can't remove /M1 from it and even explained why.

Feel free to use my design at your will. Indeed, /MREQ is reduntant. I put it just to not leave the pin connected to GND or VCC lol.

Par sd_snatcher

Prophet (3498)

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14-02-2016, 14:48

l_oliveira wrote:

Like I said, /M1 is used to make sure only I/O operations are going to cause the condition which enables the device. In a interrupt mode other than IM1 that can happen.

If the machine is kept all the time into IM1 mode, indeed there's no need to put /M1 into the logic. But we know that's not always the case.

Humm. Do you have an example of what could happen in other interrupt modes if the /M1 isn't checked?

Quote:

I just said you can't remove /M1 from it and even explained why.

Hey, chill out dude! I was still writing my reply when you posted yours. There's no way I could have seen it. Smile

Par l_oliveira

Hero (532)

Portrait de l_oliveira

14-02-2016, 14:59

http://www.z80.info/interrup.htm

The behavior of the CPU changes when it's on IM2.

"Some remarks:

"acknowledge interrupt" means pin IORQ gets together with M1-pin active/low. Furthermore the CPU adds 2 wait states to the normal machine cycle."

In IM2 during a interrupt /IORQ changes function briefly. I believe it's used by the Z80 to signal to the interrupt controller peripheral chip it want to know the ID of the device which originated the interrupt. If you don't put /M1 in the logic equation, that operation will also trigger a access hit on the device I/O port. That certainly is undesired operation.

Edit: Btw, I'm here only to help. B-)

Par l_oliveira

Hero (532)

Portrait de l_oliveira

14-02-2016, 15:22

grauw on the IRC made me notice that I overlooked part of RetroTechie comment. I apologize for that.

He mentioned that when /IORQ and /M1 are used to signal a interrutp /RD and /WR do not go low level.

By adding /M1 to the decode logic though, you relief you the worry of a spurious trigger when designing a port which toggles with just a access. There are pretty creative examples of port I/O on other computer systems or for example on the Brazilian MEGARAM which you toggle the mode by simply accessing a port with a write or a read.

On Neo Geo for example you access a register, which has A4 addess line connected as toggle input. So accessing a address with A4 low sets 0 and accessing with a address with A4 high is 1. Just mentioning (it's not like on MSX we have enough memory addresses to use such memory wasteful designs, but it saves logic on the hardware).

Par sd_snatcher

Prophet (3498)

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14-02-2016, 15:18

Yes, this is the interrupt acknowledge we and RetroTechie were talking about. But, as RetroTechie mentioned, when this event happens, both /RD and /WR will be high. This situation is already covered in your decoder, as the /Y3 output of the 74LS138 isn't connected, thus making the /M1 decoding redundant.

Par sd_snatcher

Prophet (3498)

Portrait de sd_snatcher

14-02-2016, 15:25

l_oliveira wrote:

He mentioned that when /IORQ and /M1 are used to signal a interrutp /RD and /WR do not go low level.

Yes, this is a catch in the Z80 documentation: they omitted the /RD and /WR lines from the timing charts. I also deduced it incorrectly because of that. Smile

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