Why lower bits of VDP reg#2 are filled with one's?

By WORP3

Paladin (827)

WORP3's picture

25-05-2021, 15:07

Does any of you know why the lower bits of VDP register #2 (direct set page) are filled with ones while the corresponding VDP memory address bits are zero? What is the reason or are they just described in the datasheet that they should be one's while it's actually doesn't matter at all?
Just a question out of curiosity Smile

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By Grauw

Ascended (10024)

Grauw's picture

25-05-2021, 18:33

See my comments here:

Grauw wrote:

On the V99x8, bits of table base addresses which are required to be set to 1 perform an AND operation on the table look-ups. Setting them to 0 forces those address bits to be always zero causing the table look-ups by the VDP to mirror. The most obvious use for this is in screen 4, to reduce the four pattern tables down to a single one (r#4 bits A11 and A12).

For the SAT base register, if you set bit A7 and A8 to 0 it does not affect the attribute table lookups, since it is 128 bytes and only uses A0-A6. But if you set bit A9 to 0 it moves the table down by 512 bytes to be in the same location as the colour table. That is why it must be set to 1.

The sprite colour table which uses the same base register is 512 bytes, and thus makes use of A0-A8. Setting A7 and A8 to 0 forces bits 7 and 8 of the lookup address to be 0, meaning the colours of sprites 0-7 are mirrored to (shared with) sprites 8-15, 16-23 and 24-31. Setting A9 has no effect since for the sprite colour table it is already always 0.

Grauw wrote:

A maybe clarifying illustration;

Sprite attribute table (mode 2):

Internal:   1   1   1   1   1   1   1   1   0   0  a6  a5  a4  a3  a2  a1  a0
            &   &   &   &   &   &   &   &   &   &   &   &   &   &   &   &   &
r#5 r#11: A16 A15 A14 A13 A12 A11 A10  A9  A8  A7   1   1   1   1   1   1   1

Sprite colour table (mode 2):

Internal:   1   1   1   1   1   1   1   0  a8  a7  a6  a5  a4  a3  a2  a1  a0
            &   &   &   &   &   &   &   &   &   &   &   &   &   &   &   &   &
r#5 r#11: A16 A15 A14 A13 A12 A11 A10  A9  A8  A7   1   1   1   1   1   1   1

Screen 2/4 pattern generator table:

Internal:   1   1   1   1 a12 a11 a10  a9  a8  a7  a6  a5  a4  a3  a2  a1  a0
            &   &   &   &   &   &   &   &   &   &   &   &   &   &   &   &   &
r#4:      A16 A15 A14 A13 A12 A11   1   1   1   1   1   1   1   1   1   1   1

Screen 2/4 colour table:

Internal:   1   1   1   1 a12 a11 a10  a9  a8  a7  a6  a5  a4  a3  a2  a1  a0
            &   &   &   &   &   &   &   &   &   &   &   &   &   &   &   &   &
r#3 r#10: A16 A15 A14 A13 A12 A11 A10  A9  A8  A7  A6  A5   1   1   1   1   1

Screen 5/6 pattern name table:

Internal:   1   1 a14 a13 a12 a11 a10  a9  a8  a7  a6  a5  a4  a3  a2  a1  a0
            &   &   &   &   &   &   &   &   &   &   &   &   &   &   &   &   &
r#2:      A16 A15 A14 A13 A12 A11 A10   1   1   1   1   1   1   1   1   1   1

Screen 7/8 pattern name table (note r#2 is shifted):

Internal:   1 a15 a14 a13 a12 a11 a10  a9  a8  a7  a6  a5  a4  a3  a2  a1  a0
            &   &   &   &   &   &   &   &   &   &   &   &   &   &   &   &   &
r#2:      A16 A15 A14 A13 A12 A11   1   1   1   1   1   1   1   1   1   1   1

Which bits must be 1 depend on the size of the table in the particular screen mode.

By aoineko

Master (163)

aoineko's picture

25-05-2021, 23:44

VDP register #2 is not the only one that requires masks of 1s for certain screen modes; registers #3, #4 and #5 are also concerned.
Here is a table with all the VDP registers value restrictions I know of (for MSX 1 & 2):

By PingPong

Prophet (3756)

PingPong's picture

26-05-2021, 00:24

here? where?

By Arjan

Paladin (736)

Arjan's picture

26-05-2021, 08:38

The image is served from http instead of https: http://msxvillage.fr/upload/screenmodetables_7df56.jpg

By WORP3

Paladin (827)

WORP3's picture

26-05-2021, 10:12

Wow there is more to these bits then I could have expected Smile
Thanks for the extensive explanation!