One chip MSX improvement project

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By caro

Champion (512)

caro's picture

31-03-2013, 17:12

Ace wrote:

I do have a preliminary diagram I put together from the service manual of the Goldstar FC-200 for possibly hooking up the real AY-3-8910 to the DE0. If that will be of some use to you, I can provide it for you.

Keep in mind that external AY must only work in the WRITE mode ports.
READ ports will work AY, built-in FPGA.

By Ace

Resident (53)

Ace's picture

31-03-2013, 17:47

caro wrote:
Ace wrote:

I do have a preliminary diagram I put together from the service manual of the Goldstar FC-200 for possibly hooking up the real AY-3-8910 to the DE0. If that will be of some use to you, I can provide it for you.

Keep in mind that external AY must only work in the WRITE mode ports.
READ ports will work AY, built-in FPGA.

This would mean BC1 and BDIR hooked up to +5V and BC0 to Ground? Looking at the datasheet, this corresponds to WRITE TO PSG, so this might be it. Correct me if I'm wrong.

Also tried out your latest update, and this is progressively getting better. Metal Gear no longer has that obnoxious noise, the missing noise is back (though Eggerland has the high-pitched noise again, which I'm gonna have to check at what frequency it's at), but I made a mistake with the volume levels of the SCC and AY-3-8910. With current volume levels, the AY-3-8910 is still a little loud, which is fixed by pressing SHIFT-F9 twice. The default volume level of the AY-3-8910 should be adjusted accordingly.

The noise is still inaccurate, though. There's a noticeable difference between the noise of the FPGA-simulated AY-3-8910 and that of the real chip.

EDIT: Forgot one thing. The audio out of the DE0 tends to get garbled when the overall volume level is maxed out. Maximum volume should probably be limited to one notch below the current maximum.

By caro

Champion (512)

caro's picture

31-03-2013, 18:14

Ace wrote:

This would mean BC1 and BDIR hooked up to +5V and BC0 to Ground? Looking at the datasheet, this corresponds to WRITE TO PSG, so this might be it. Correct me if I'm wrong.

BDIR  BC2  BC1
---------------
0      1     0   -   Not Aktiv
1      1     0   -   WR DAT
1      1     1   -   WR Adress
0      1     1   -   RD Dat (prohibit)
---------------

By Ace

Resident (53)

Ace's picture

31-03-2013, 18:22

I completely mislabeled the control pins on the AY-3-8910 save for BDIR. But looking at this, I'm quite certain the AY-3-8910 would need to be in WR DAT mode to work correctly on the DE0. Is this correct?

By caro

Champion (512)

caro's picture

31-03-2013, 18:51

We need to ensure the execution of commands WR ADRESS and WR DAT.

By vanfanel

Champion (446)

vanfanel's picture

02-04-2013, 13:32

Ace wrote:

EDIT: Forgot one thing. The audio out of the DE0 tends to get garbled when the overall volume level is maxed out. Maximum volume should probably be limited to one notch below the current maximum.

Audio out of the DE1 is also garbled when the overall volume level is maxed out. I also think maximum it should be limited.

By Ace

Resident (53)

Ace's picture

21-04-2013, 00:53

Okay, so I built an AY-3-8910 circuit for the DE0 and I'm not getting anywhere with this. The DE0 refuses to boot and the 7-segment display shows FF7F. What does this mean? All I know is the problem comes from something on GPIO0 as when I remove the ribbon cable, the MSX boots. Also, the DE0 cannot supply enough current to work with the AY-3-8910 circuit as the entire DE0 fails to power on if I use the 5V rail on the GPIO header to power the AY-3-8910 and the 4 chips around it (74LS138, 74LS02, 74LS04 and 74LS00). What would prevent the DE0 from booting when I have the circuit in place and the GPIO0 header connected to the board?

By Ace

Resident (53)

Ace's picture

21-04-2013, 02:41

The problem appears to be coming from the AY-3-8910 itself. If I remove the chip out of its socket, the computer boots fine, but as soon as the AY-3-8910 is in there, the DE0 fails to boot. If I insert the chip while the DE0 is powered on, it crashes. Is this AY-3-8910 dead? Or is this chip fake? The markings are coming off just by me rubbing my thumb on the chip and it's dated 0916, week 16 of 2009. I highly doubt the AY-3-8910 was in production in 2009 (this is a chip marked GI).

By RetroTechie

Paragon (1563)

RetroTechie's picture

21-04-2013, 03:23

Ace wrote:

This would mean BC1 and BDIR hooked up to +5V and BC0 to Ground? Looking at the datasheet, this corresponds to WRITE TO PSG, so this might be it. Correct me if I'm wrong.

If my info is correct, the usual config would be:

  • Address lines and /IORQ produce an active-low '/CS' signal for the PSG.
  • NORed with A0, this gives BC1 signal.
  • NORed with A1, this gives BDIR signal.
  • BC2 input is wired to +5V.

See for example Sony HB-55/75 schematic how it's done. You can work out for yourself what possible combinations there are, and into what PSG bus behavior it translates.

FWIW: I'd think working out DE0 audio output, and producing a proper signal for that, is easier than hooking up an antique PSG chip? But what do I know... LOL!

By Ace

Resident (53)

Ace's picture

21-04-2013, 04:15

I just want to use the original audio hardware as I'm particularly picky about audio more than anything else. For me, it's simpler to do this as I know no VHDL, but have a lot of experience building various electronic circuits.

From what I saw in the service manual of the Goldstar FC200, the circuit for the AY-3-8910 to work is this:

-Address lines A3, A4 and A5 to pins 1, 2 and 3 of a 74LS138 respectively
-/IORQ NORed with A6 to pin 6 of a 74LS138
-Pin 5 of the 74LS138 tied to Ground
-A7 NANDed with /M1 to pin 4 of a 74LS138
-Pin 11 of the 74LS138 NORed with A0 to pin 29 of the AY-3-8910
-BC2 and A8 tied to VCC
-/A9 tied to Ground

Going from what Caro said, the circuitry for BDIR can be omitted as the two write modes for the AY-3-8910 have BDIR high, so that would be tied to VCC.

I'll go find the service manual for the HB-55/75 and see how Sony did it in that computer.

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