NES and Famicom support for the One-Chip-MSX!

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By syntax_error

Resident (51)

syntax_error's picture

13-10-2007, 21:22

video game system development kit

http://www.xgamestation.com/media.php

By AuroraMSX

Paragon (1901)

AuroraMSX's picture

14-10-2007, 10:47

video game system development kit

http://www.xgamestation.com/media.phpAnd this relates to MSX or the OCM... how?

As far as I can tell from that website it's just a home-computer-like development board with an ARM7 processor - incompatible to any 8-bit system known to man...

(Note to site admin: auto-url + quote closing tag = trouble)

By tcdev

Expert (76)

tcdev's picture

19-10-2007, 17:52

The OCM asserts the Z80 wait pin when it's busy accessing memory - I have no idea if that's what the real MSX does or not, but if not it certainly won't be cycle accurate.

I've been playing with the NES design lately (I've managed to get Tennis running) and have discovered that the CPU clock is actually derived from the 21MHz PPU clock - so the CHR & PRG bus accesses should be synchronous - or there-abouts. I suspect the reason it didn't look like that on the CRO was that the PRG access timing differed depending on the actual instruction being executed... I'll have to go back and look at it again...

Anyway the upshot is that it should be possible to schedule PRG (CPU) and CHR (PPU) accesses on a regular basis from an FPGA design. Not sure if the memory bandwidth is there on the OCM SDRAM (when you add refresh cycles) - haven't done the calculations. Was also interested to learn that the CPU is halted when doing sprite DMA!

For those interested, my NES implementation is complete only to the point where it can run Tennis, and perhaps a few other simple carts, with no scrolling and no mappers. It uses >28KB of internal FPGA memory (EP2C35) so IIRC it can't be ported to the OCM (EP1C12) as-is - not that I have one anyway. It _might_ just fit with external CPU RAM (2KB)???

Regards,
Mark

By DamageX

Master (217)

DamageX's picture

20-10-2007, 08:16

Was also interested to learn that the CPU is halted when doing sprite DMA!
Yes it is actually the CPU that is transferring the data, the video chip just accepts it as usual. So it is not really "DMA" but just a block memory move feature that Nintendo put in their CPU.

By tcdev

Expert (76)

tcdev's picture

20-10-2007, 15:41

Interesting. I assumed it was an external function, likely the PPU itself. But looking at the register address, the sprite DMA function is in the same block as the APU functions, so I guess that's right. Not that it matters, but I implemented the sprite DMA in an external process, which de-asserts the 6502 RDY pin whilst in progress. And it too mimics CPU writes to normal sprite registers. Most importantly I suppose is the fact that the DMA on a real NES takes 513 cpu cycles, as does mine.

Of course, whilst Tennis looks like it's running on a NES, internally it resembles nothing of the sort. In fact, I based the design off my Centipede implementation of all things! Actually turned out to be a good choice - I chose it originally because it had a 6502 but - unlike most other video games - Centipede sprites are only 8 pixels high, just like NES Tennis.

By TaylorsEverythingChannel

Master (162)

TaylorsEverythingChannel's picture

24-09-2020, 05:43

I would like to see a possible NES emulator or loader, it can be either COM or ROM cart, but I'm very interested. I think there might be one mentioned in here, I will check soon.

By TaylorsEverythingChannel

Master (162)

TaylorsEverythingChannel's picture

21-10-2020, 18:35

OMG. You're right, while doing a NES to PC Engine conversion, I was able to capture this.
Image contains hex with DB 99.

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