CAS signal in SVI 738 or MSX in general

some info from IBM about DRAM

There are only a few signals that control the operation of a DRAM.
Row Address Select (Strobe) (RAS) The RAS circuitry is used to latch the row address and to initiate
the memory cycle. It is required at the beginning of
every operation. RAS is active low; that is, to enable
RAS, a transition from a high voltage to a low voltage level is required. The voltage must remain low
until RAS is no longer needed. During a complete
memory cycle, there is a minimum amount of time
that RAS must be active (tRAS), and a minimum
amount of time that RAS must be inactive, called the
RAS precharge time (tRP). RAS may also be used to
trigger a refresh cycle (RAS Only Refresh, or ROR).
Column Address Select (Strobe) (CAS) CAS is
used to latch the column address and to initiate the
read or write operation. CAS may also be used to
trigger a CAS before RAS refresh cycle. This refresh
cycle requires CAS to be active prior to RAS and to
remain active for a specified time. It is active low.
The memory specification lists the minimum amount
of time CAS must remain active (tCAS) to initiate a
read or write operation. For most memory operations, there is also a minimum amount of time that
CAS must be inactive, called the CAS precharge
time (tCP). (An ROR cycle does not require CAS to
be active.)
Address The addresses are used to select a memory location on the chip. The address pins on a
memory device are used for both row and column
address selection (multiplexing). The number of
addresses depends on the memory’s size and organization. The voltage level present at each address
at the time that RAS or CAS goes active determines
the row or column address, respectively, that is
selected. To ensure that the row or column address
selected is the one that was intended, set up and
hold times with respect to the RAS and CAS transitions to a low level are specified in the DRAM timing
specification.
Write Enable (WE) The write enable signal is used
to choose a read operation or a write operation. A
low voltage level signifies that a write operation is
desired; a high voltage level is used to choose a
read operation. The operation to be performed is
usually determined by the voltage level on WE when
CAS goes low (Delayed Write is an exception). To
ensure that the correct operation is selected, set up
and hold times with respect to CAS are specified in
the DRAM timing specification.
Output Enable (OE) During a read operation, this
control signal is used to prevent data from appearing
at the output until needed. When OE is low, data
appears at the data outputs as soon as it is available. OE is ignored during a write operation. In many
applications, the OE pin is grounded and is not used
to control the DRAM timing.

Yes but I will just use 2 x 44256 DRAM and try to keep it simple - all glue logic are TTL LS chips that will be replace by CPLD
I try to solve the SVI expansion clue - Henrik Gilvad successfully upgrade alot of does machines from 256 to 1MB so it possible but no info exist

I will try to keep on solving the clue ... I know alot of user have upgrade there machine to MSX2+, so could I solved this I will publish the schematics, and order som PCB for does that do not want to make the hack themselfs

The plan is to remove LS157 + 8 dram (original 64kb) and reuse signal from does pins to the addon card

I bet something died... but would be interesting to know if it was machine, user or project.

By the way, upgrading to MSX 2+ is easy too.
Try to find the several ways to do it in the Internet (they used to be in Hans Otten site).
And always get the schematics, so you can figure out how to improve any upgrade arround.

I tried the clock-chip upgrade, but it did not worked for me, as it seems to be different versions of the board.
Maybe I will try in the future.

some images, I got the clock stuff and the msx2+ and msx2 to work, but still working on mapping memory and f4 port fix for msx2+ upgrade

so more input will come :) as soon I find time for it ;) ;) ;)