Textured raycasting TMS9918A

Page 3/5
1 | 2 | | 4 | 5

By ARTRAG

Enlighted (6506)

ARTRAG's picture

17-08-2020, 11:24

geijoenr wrote:

oh it must be this one

https://github.com/Rasmus-M/raycaster

Actually the code with the texture mapping is here
https://github.com/Rasmus-M/raycaster/tree/texture_mapped

Anyone willing to try a Z80 port?
BTW, the TMS9900 has opcodes for 16x16=32 bit multiplications and 32 bit divisions..

This could be a bottleneck for direct port of the current TI99/4A implementation

https://web.archive.org/web/20110221025303/http://www.bitsav...

By geijoenr

Master (254)

geijoenr's picture

17-08-2020, 19:01

Yeah, the code has many instances of "mpy" and "div", which is a bit of a bummer. I am not sure just trying to translate the code to z80 is a wise approach because all the arithmetic is 16bit... but oh well, is not a lot of code. And if z80 cannot lift it at least is a reality check.

By PingPong

Prophet (3737)

PingPong's picture

17-08-2020, 21:07

Mpy require 52 cycles
Div from 16 to 124 cycles
Plus there are memory cycles.
Faster than could the z80 can do via sw but not so fast

By santiontanon

Paragon (1416)

santiontanon's picture

17-08-2020, 22:39

I think all of those multiplications/divisions should be changed into pre-calculated tables on the MSX implementation, which can accelerate things further. I haven't looked at the source code, but do those operations need to be 16 bit precision? It seems that the demo advances block by block, so, lowering the resolution of the x/y coordinates can reduce the size of the pre-calculated tables.

By ARTRAG

Enlighted (6506)

ARTRAG's picture

18-08-2020, 02:46

I think that the step of movement depends on speed. At max speed it is one map square, but it can be much smaller

By Metalion

Paragon (1373)

Metalion's picture

19-08-2020, 11:45

PingPong wrote:

Mpy require 52 cycles
Div from 16 to 124 cycles
Plus there are memory cycles.
Faster than could the z80 can do via sw but not so fast

MPY can multiply 16 bits registers into a 32-bit result.
Achieving that on Z80 takes 1000+ cycles ..... (see http://z80-heaven.wikidot.com/math#toc4)

By Parn

Hero (644)

Parn's picture

19-08-2020, 14:54

HRA! just released an OCM firmware with a pumped up Z80 with multiplication instructions. And there's the turboR as well. Tongue

By ducasp

Champion (431)

ducasp's picture

19-08-2020, 15:14

Parn wrote:

HRA! just released an OCM firmware with a pumped up Z80 with multiplication instructions. And there's the turboR as well. Tongue

As far as I know the MUL instructions are supported by KdL OCM's build for quite a while as well... Sure HRA! is working on a lot of other Turbo-R related stuff, but MUL instructions are on OCM's for quite a while, not sure if you need to load the Turbo-R BIOS from SD to enable them though, would need to check FPGA code. Wink

By Grauw

Ascended (9900)

Grauw's picture

19-08-2020, 18:32

Unless that raycaster code is swamped with multiplications, probably the extra time the Z80 spends in a few multiplications here and there will be easily compensated by the time gained due to not having to deal with the TI-99/A’s notoriously complicated memory architecture.

By PingPong

Prophet (3737)

PingPong's picture

19-08-2020, 19:43

Grauw wrote:

Unless that raycaster code is swamped with multiplications, probably the extra time the Z80 spends in a few multiplications here and there will be easily compensated by the time gained due to not having to deal with the TI-99/A’s notoriously complicated memory architecture.

and there is also a little faster vdp access due to no hw delay imposed on msx1 arch. on tms the vdp access is, if i remember correctly, more slower due to hw waits.

Page 3/5
1 | 2 | | 4 | 5