Multiplayer link cable

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By aoineko

Paragon (1138)

aoineko's picture

27-05-2023, 17:06

Danjovic wrote:

You can fiddle with the following circuit and experience the reaction of the logic levels at register 14 while you click on the H /L labels on the register 15 to change logic levels.
[...]

Thank you Danjovic for this playful explanation!
Starting to make sense. ^^

So putting R#15's bit0 to 0 on one machine, could be detected on R#14's bit4 of the other machine.
I imagine that all the bits from 0 to 5 of R#14 go to 0 in this case.

@CJS was talking about "port" 14 and 15, should I read this as registers 14 and 15?
Or is it something else?

An important piece of information for which I haven't had an answer: are there any emulators that emulate 2 (or more) MSXs linked by an F1Spritit3D/JoyNet-type cable?
In the openMSX development log, this feature was added and then removed. Are there any plans to add it again?
Are there any other emulators that emulate this cable?

By cjs

Master (143)

cjs's picture

28-05-2023, 11:56

aoineko wrote:

@CJS was talking about "port" 14 and 15, should I read this as registers 14 and 15?

Yes. I should have said "register 14" and "register 15" to be more clear.

aoineko wrote:

So putting R#15's bit0 to 0 on one machine, could be detected on R#14's bit4 of the other machine.
I imagine that all the bits from 0 to 5 of R#14 go to 0 in this case.

Nope. You'll note that only the two pins 6 are connected above, so in R14 the only bit that will change due to bringing R15.0 low is R14.4, which is the only bit in R14 connected to pin 6.

R14.0 through R14.3 should always remain low, since nothing is connected to pins 1-4. R14.5 will be high unless you set R15.1 low, in which case, both being internally connected together at pin 6, R14.5 will read low.

(This all assumes that you're doing your reading with R15.6 low, to select port 1, and plugging your cable into port 1, of course.)

By Danjovic

Champion (344)

Danjovic's picture

31-05-2023, 22:22

An sketch of a protocol, inspired in CAN with two data lines on trigger pins (6,7) and a third bidirectional data line (ATT) made out of a diode from pin 8 to pin 1.
This bus Idles with both data lines in HIGH and the ATT line in LOW.

The station who wants to transmit, drop both data lines and releases its ATT line, then wait for all the stations to release their ATT lines which can be recognized by the ATT line going High. This marks the end of the SYNC phase. After that, station 1 starts to transmit its address.
In the example, Station 2 have data to transmit, and after recognize the end of the SYNC phase it start to transmit its address.
The address is put on the DATA lines at the same time the ATT line is held down, and then the sender rises its ATT line and waits for the the level on ATT line to go high, then sample the resulting value (Y0/Y1, Y2/Y3....
The senders must compare the values written on the bus (D0/D1, D2/D3....) with the values read back (Y0/Y1, Y2/Y3....) to check if they won the arbitration. The one with smaller ID wins. This is done every 2 bits of addressing.
The station who won the arbitration keeps sending addressing data, while the one who lost the arbitration enters in "listen mode", while releasing the levels on its data line.
After the Addressing phase, the data are sent at every change of the ATT line, commanded by the station who won the arbitration. The example shows 2 bytes of data for didatic purposes.
At the end of the packet the sender releases its data lines and hold down the ATT line, returning the bus to Idle state.
After that, Station 2 that still have data to transmit, can initiate another bus cycle.

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