Is it possible to create an ASCII16 megarom switching off the bios and using page0 as ROM or eventually RAM where we will copy our code, included a new interrupt handler?
if it is possible, how to modify the classic ASCII16 megarom init code?
The page0 ROM option I don't think is possible with standard mappers. I don't see a problem with switching the BIOS off and using only RAM in page0; as long as you implement an interrupt handler.
Use ram. Disable interrupts, put ram in page0, copy your data there from your rom and re-enable interrupts.
If you place at 38h a proper interrupt handler everything should go without problems
In the isr make sure to save the registers you use and to read the status register 0 to enable the next interrupt
Yep, I have already a ready isr. I used it when I converted my Earth Attack to sg-1000 wich has no bios. So it was pretty easy, starting code from 0000h.
Or use WRSLT to poke a jp continue_address at RAM addresses 0-2, and then CALSLT to address 0 of the RAM slot. This will select the RAM in page 0 and call the jump, which will then jump back into your ROM code outside of page 0 to continue. But from then on RAM will be enabled in page 0 and you can go on and initialise it by copying program code and data from your ROM.
This way you don’t need to write custom slot selection code, which is often difficult to get right because the mechanics of dealing with subslots is a bit complex, and people tend to primarily test it with primary slots and don’t cover all the possible configurations that people are using. And if you want to return back to the normal BIOS state on program exit, just return.
Personally I think this is a very elegant way to do it.
Is it possible to create an ASCII16 megarom switching off the bios and using page0 as ROM or eventually RAM where we will copy our code, included a new interrupt handler?
It's possible when there are mirrors (when the bit 15 of the address is ignored).
Or use WRSLT to poke a jp continue_address at RAM addresses 0-2, and then CALSLT to address 0 of the RAM slot. This will select the RAM in page 0 and call the jump, which will then jump back into your ROM code outside of page 0 to continue. But from then on RAM will be enabled in page 0 and you can go on and initialise it by copying program code and data from your ROM.
This way you don’t need to write custom slot selection code, which is often difficult to get right because the mechanics of dealing with subslots is a bit complex, and people tend to primarily test it with primary slots and don’t cover all the possible configurations that people are using. And if you want to return back to the normal BIOS state on program exit, just return.
Personally I think this is a very elegant way to do it.
So bios will be already switched off? Then, before doing a CALSLT, is better to WRTSLT also the new isr at 38h? (I think I've seen something like this when looking at smw source, but it was some time ago so I'm not sure)
Or use WRSLT to poke a jp continue_address at RAM addresses 0-2, and then CALSLT to address 0 of the RAM slot.
If you preload hl (assuming you don't need to pass something using hl) with continue_address before CALSLT you only need put a jp (hl) at address 0.
thegeps wrote:
So bios will be already switched off? Then, before doing a CALSLT, is better to WRTSLT also the new isr at 38h? (I think I've seen something like this when looking at smw source, but it was some time ago so I'm not sure)
CALSLT disables interrupts - so you can copy your ISR afterwards, then re-enable them.
