I think also the cpu overhead of this ‘solution’ has to be taken into account . Having an interrupt for every out/in, then running some code from NMI can have some serious performance impact .
Additionally, the suggested architecture for pretecting memory could protect memory mappers (since the management is I/O based), but completely fails protecting MSX SLOTs.
The guy had an epiphany on how to implement protected systems based on 8-bit CPUs, but it would only apply to a new system made with that purpose. For our old architectures it is just useless.
Yeah I agree, the content of the video is cool, but protected mode is not a feature of the CPU itself, like for example the embedded memory refresh controller and the ghost register set (invoked by exx/ ex af,af').
But hey, at 01:31 one the computers shown is a SHARP Hotbit HB-8000 and that alone already earned my LIKE!
Too bad he hasn't built an actual system yet, so we can judge its feasibility. But I like his outside-of-the-box thinking. As a concept, it may even excite me more than MSX3, which seems so disconnected from existing hardware.
I think also the cpu overhead of this ‘solution’ has to be taken into account . Having an interrupt for every out/in, then running some code from NMI can have some serious performance impact .
one of the reasons that justify the absesce of a protected mode is that those early processors have too little horse power to efficiently support multitasking even if sybos proved that that can be done.
